cystech electronics corp. spec. no. : c944f3 issued date : 2014.06.09 revised date : 2015.09.04 page no. : 1/9 MTE010N10F3 cystek product specification n-channel enhancement mode power mosfet MTE010N10F3 features ? low gate charge ? simple drive requirement ? repetitive avalanche rated ? fast switching characteristic ? rohs compliant package symbol outline ordering information device package shipping MTE010N10F3-0-t7-x to-263 (pb-free lead plating and rohs compliant package) 800 pcs / tape & reel MTE010N10F3 to-263 g gate d drain s source bv dss 100v i d @ t c =25 c, v gs =10v (silicon limit) 70a r dson(typ) @ v gs =10v, i d =50a 9.6m 10.1m r dson(typ) @ v gs =7v, i d =20a g d s environment friendly grade : s for rohs compliant products, g for rohs compliant and green compound products packing spec, t7 : 800 pcs / tape & reel, 13? reel product rank, zero for no rank products product name
cystech electronics corp. spec. no. : c944f3 issued date : 2014.06.09 revised date : 2015.09.04 page no. : 2/9 MTE010N10F3 cystek product specification absolute maximum ratings (t c =25c, unless otherwise noted) parameter symbol limits unit drain-source voltage v ds 100 gate-source voltage v gs 20 v continuous drain current @ t c =25 c, v gs =10v(silicon limit) 70 continuous drain current @ t c =100 c, v gs =10v(silicon limit) 50 continuous drain current @ t c =25 c, v gs =10v(package limit) (note 1) i d 60 pulsed drain current (note 3) i dm 300 continuous drain current @ t a =25 c (note 2) 8 continuous drain current @ t a =70 c (note 2) i dsm 6.5 avalanche current (note 3) i as 80 a avalanche energy @ l=100 h, i d =80a, r g =25 (note 2) e as 320 repetitive avalanche energy@ l=0.1mh (note 3) e ar 15 mj t c =25 c (note 1) 150 power dissipation t c =100 c (note 1) p d 75 w t a =25 c (note 2) 2 power dissipation t a =70 c (note 2) p dsm 1.3 w operating junction and storage temperature tj, tstg -55~+175 c thermal data parameter symbol value unit thermal resistance, junction-to-case, max r th,j-c 1 thermal resistance, junction-to-ambient, max, t 10s (note 1) 15 thermal resistance, junction-to-ambient, max (note 1) r th,j-a 62.5 c/w note : 1 . the power dissipation p d is based on t j(max) =175 c, using junction-to-case thermal resistance, and is more useful in setting the upper di ssipation limit for cases where additional heatsinking is used. 2 . the value of r ja is measured with the device mounted on 1 in 2 fr-4 board with 2 oz. copper, in a still air environment with t a =25 c. the power dissipation p dsm is based on r ja and the maximum allowed junction temperature of 150 c. the value in any given application depends on the user?s specific board design, and the maximum temperature of 175 c may be used if the pcb allows it. 3 . repetitive rating, pulse width limited by junction temperature t j(max) =175 c. ratings are based on low frequency and low duty cycles to keep initial t j =25 c. 4. the maximum current limited by package is 60a. 5. the static characteristics are obtained using <300 s pulses, duty cycle 0.5% maximum. 6. the r ja is the sum of thermal resistance from junction to case r jc and case to ambient.
cystech electronics corp. spec. no. : c944f3 issued date : 2014.06.09 revised date : 2015.09.04 page no. : 3/9 MTE010N10F3 cystek product specification characteristics (t c =25 c, unless otherwise specified) symbol min. typ. max. unit test conditions static bv dss 100 - - v gs =0v, i d =250 a v gs(th) 2.0 2.9 4.0 v v ds = v gs , i d =250 a g fs - 41 - s v ds =5v, i d =20a i gss - - 2 100 na v gs = 2 20v - - 1 v ds =80v, v gs =0v i dss - - 25 a v ds =80v, v gs =0v, tj=55 c - 9.6 13.5 v gs =10v, i d =50a *r ds(on) - 10.1 15.8 m v gs =7v, i d =20a dynamic *qg - 48 - *qgs - 20 - *qgd - 10 - nc i d =20a, v ds =50v, v gs =10v *t d(on) - 19 - *tr - 12 - *t d(off) - 35 - *t f - 11 - ns v ds =50v, i d =20a, v gs =10v, r g =3 ciss - 3753 - coss - 250 - crss - 65 - pf v gs =0v, v ds =30v, f=1mhz source-drain diode *i s - - 70 a *v sd - 0.89 1.2 v i s =50a, v gs =0v *trr - 90 - ns *qrr - 135 - nc i f =20a, v gs =0v, di f /dt=100a/ s *pulse test : pulse width 300 s, duty cycle 2%
cystech electronics corp. spec. no. : c944f3 issued date : 2014.06.09 revised date : 2015.09.04 page no. : 4/9 MTE010N10F3 cystek product specification typical characteristics typical output characteristics 0 50 100 150 200 250 300 0246810 v ds , drain-source voltage(v) i d , drain current(a) 10v,9v,8v,7v v gs = 5v v gs = 4v v gs =6v brekdown voltage vs junction temperature 0.4 0.6 0.8 1 1.2 1.4 -75 -50 -25 0 25 50 75 100 125 150 175 tj, junction temperature(c) bv dss , normalized drain-source breakdown voltage i d =250 a, v gs =0v static drain-source on-state resistance vs drain current 1 10 100 0.1 1 10 100 i d , drain current(a) r ds(on) , static drain-source on-state resistance(m) v gs =6v v gs =7v v gs =10v v gs =4.5v reverse drain current vs source-drain voltage 0.2 0.4 0.6 0.8 1 1.2 04812162 i dr , reverse drain current(a) v sd , source-drain voltage(v) 0 tj=25c tj=150c static drain-source on-state resistance vs gate-source voltage 0 10 20 30 40 50 60 70 80 90 100 024681 0 drain-source on-state resistance vs junction tempearture 0 0.4 0.8 1.2 1.6 2 2.4 -75 -50 -25 0 25 50 75 100 125 150 175 tj, junction temperature(c) r ds(on) , normalized static drain- source on-state resistance v gs =10v, i d =20a r ds( on) @tj=25c : 9.6m v gs , gate-source voltage(v) r ds(on) , static drain-source on- state resistance(m) i d =20a
cystech electronics corp. spec. no. : c944f3 issued date : 2014.06.09 revised date : 2015.09.04 page no. : 5/9 MTE010N10F3 cystek product specification typical characteristics(cont.) capacitance vs drain-to-source voltage 100 1000 10000 0.1 1 10 100 v ds , drain-source voltage(v) capacitance---(pf) c oss ciss crss threshold voltage vs junction tempearture 0.4 0.6 0.8 1 1.2 1.4 -75 -50 -25 0 25 50 75 100 125 150 175 tj, junction temperature(c) v gs(th) , normalized threshold voltage i d =250 a i d =1ma forward transfer admittance vs drain current 0.01 0.1 1 10 100 0.001 0.01 0.1 1 10 100 i d , drain current(a) g fs , forward transfer admittance(s) v ds =5v pulsed ta=25c gate charge characteristics 0 2 4 6 8 10 0 102030405060 total gate charge---qg(nc) v gs , gate-source voltage(v) i d =20a v ds =80v v ds =50v v ds =20v maximum safe operating area 0.1 1 10 100 1000 0.1 1 10 100 1000 v ds , drain-source voltage(v) i d , drain current(a) dc 10ms 100ms 1ms 100 s 10 s r ds( on) limit t c =25c, tj=175c, v gs =10v,r jc =1c/w single pulse maximum drain current vs case temperature 0 10 20 30 40 50 60 70 80 0 25 50 75 100 125 150 175 200 t c , case temperature(c) i d , maximum drain current(a) v gs =10v, r jc =1c/w package limit silicon limit
cystech electronics corp. spec. no. : c944f3 issued date : 2014.06.09 revised date : 2015.09.04 page no. : 6/9 MTE010N10F3 cystek product specification typical characteristics(cont.) typical transfer characteristics 0 50 100 150 200 250 300 0246810 v gs , gate-source voltage(v) i d , drain current (a) v ds =10v single pulse maximum power dissipation 0 500 1000 1500 2000 2500 3000 3500 4000 4500 5000 0.0001 0.001 0.01 0.1 1 10 pulse width(s) peak transient power (w) t j(max) =175c t c =25c ja =1c/w transient thermal response curves 0.01 0.1 1 1.e-05 1.e-04 1.e-03 1.e-02 1.e-01 1.e+00 1.e+01 t 1 , square wave pulse duration(s) r(t), normalized effective transient thermal resistance single pulse 0.01 0.02 0.05 0.1 0.2 d=0.5 1.r jc (t)=r(t)*r jc 2.duty factor, d=t 1 /t 2 3.t jm -t c =p dm *r jc (t) 4.r jc =1 c/w
cystech electronics corp. spec. no. : c944f3 issued date : 2014.06.09 revised date : 2015.09.04 page no. : 7/9 MTE010N10F3 cystek product specification reel dimension carrier tape dimension
cystech electronics corp. spec. no. : c944f3 issued date : 2014.06.09 revised date : 2015.09.04 page no. : 8/9 MTE010N10F3 cystek product specification recommended wave soldering condition product peak temperature soldering time pb-free devices 260 +0/-5 c 5 +1/-1 seconds recommended temperature profile for ir reflow profile feature sn-pb eutectic assembly pb-free assembly average ramp-up rate (tsmax to tp) 3 c/second max. 3 c/second max. preheat ? temperature min(t s min) ? temperature max(t s max) ? time(ts min to ts max ) 100 c 150 c 150 c 200 c 60-120 seconds 60-180 seconds 183 c 60-150 seconds time maintained above: ? temperature (t l ) ? time (t l ) 217 c 60-150 seconds peak temperature(t p ) 240 +0/-5 c 260 +0/-5 c time within 5 c of actual peak temperature(tp) 10-30 seconds 20-40 seconds ramp down rate 6 c/second max. 6 c/second max. time 25 c to peak temperature 6 minutes max. 8 minutes max. note : all temperatures refer to topside of the package, measured on the package body surface.
cystech electronics corp. spec. no. : c944f3 issued date : 2014.06.09 revised date : 2015.09.04 page no. : 9/9 MTE010N10F3 cystek product specification to-263 dimension style : pin 1.gate 2.drain 3.source 3-lead plastic surface mounted package cystek package code : f3 marking : e010 n10 device name date code *:typical inches millimeters inches millimeters dim min. max. min. max. dim min. max. min. max. a 0.3800 0.4050 9.65 10.29 i 0.0500 0.0700 1.27 1.78 b 0.3300 0.3700 8.38 9.40 j - *0.1000 - *2.54 c - 0.0550 - 1.40 k 0.0450 0.0550 1.14 1.40 d 0.5750 0.6250 14.61 15.88 l 0.0200 0.0390 0.51 0.99 e 0.1600 0.1900 4.06 4.83 1 - - 6 8 f 0.0450 0.0550 1.14 1.40 2 - - 6 8 g 0.0900 0.1100 2.29 2.79 3 - - 0 5 h 0.0180 0.0290 0.46 0.74 notes : 1.controlling dimension : millimeters. 2.maximum lead thickness includes lead finish thickness, and minimum lead thickness is the minimum thickness of base material. 3.if there is any question with packing spec ification or packing method, please cont act your local cystek sales office. material : ? lead : pure tin plated. ? mold compound : epoxy resin family, flammability solid burning class:ul94v-0. important notice: ? all rights are reserved. reproduction in whole or in part is prohibited without the prior written approval of cystek. ? cystek reserves the right to make changes to its products without notice. ? cystek semiconductor products are not warranted to be suitab le for use in life-support applications, or systems. ? cystek assumes no liability for any consequence of customer pr oduct design, infringement of pat ents, or application assistance . a b c d 123 k l j g h e f 2 1 2 3 i
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